A clock and data recovery (CDR) loop is used to recover an embedded clock from an incoming data stream. In many communication systems, only a data signal is transmitted. The receivers in such systems must generally recover a clock signal from the data signal. Conventional CDR circuits are generally designed to recover a clock signal within a narrow, and generally constant, range of frequencies. However, spread spectrum clock (SSC) generation is being increasingly used in data communication. SSC is generally a form of frequency modulation. The instantaneous frequency may be represented as a function of time, and is usually a periodic function that may be characterized as a modulation profile.
Spectrum spreading is commonly used in radio frequency communication to facilitate high-resolution ranging, multiple access, jamming resistant waveforms, and energy density reduction. Spread spectrum clock generation has also been adopted in many high speed data communications standards, including the PCIe and SATA standards.
Spread spectrum clocking is particularly useful for reducing electromagnetic interference (EMI). Electronic devices typically generate electromagnetic interference (EMI) when operating. The EMI generated by one electronic device may adversely affect the operation of another electronic device. In order to minimize adverse effects of EMI on other electronic devices, regulatory agencies in many countries have adopted standards which limit the amount of energy an electronic device may radiate at any given frequency.
Electronic devices frequently use a clock signal of some frequency for operation. In many such devices, relatively long traces or wires are used to route the clock signal to various integrated circuit (IC) components. These long wires or traces can act as antennas which, in turn, radiate energy at the clock signal frequency and (in many cases) its harmonics. Since antennas radiate more efficiently as wavelength becomes smaller with respect to antenna length, the amount of energy so radiated increases as the clock frequency increases. Consequently, in sophisticated electronic devices such as, for instance, personal computers, printers, cellular phones and peripheral devices, where clock frequencies are approaching gigahertz speeds, EMI is increasingly problematic.
When substantially all of a clock's energy is at one frequency, EMI energy may exceed regulatory limits at that clock frequency. Referring now to FIG. 1A, EMI profile 101 shows the emissions of a device at a substantially constant clock speed. A well known technique to reduce the peak EMI energy at the clock frequency (and its harmonics) is to use spread spectrum clock generation techniques to spread the energy across a part of the frequency spectrum. EMI profile 102 shows the reduced maximum emissions for a device with a spread spectrum clock.
Different modulation profiles can be used to achieve spread spectrum clocking, with varying results in terms of emission profiles. Referring now to FIG. 1B, emission profile 111 shows the emissions resulting from a non-linear optimized modulation profile (e.g., the modulation profile shown in FIG. 2B). Emission profile 112 shows the emissions resulting from a triangular modulation profile (e.g., the modulation profile shown in FIG. 2A). Emission profile 113 shows the emissions resulting from a sinusoidal modulation profile. Other periodic waveforms may be chosen by different implementers. Furthermore, different modulation waveforms may result from imperfect implementations of SSC generators. Therefore it is desirable to recover clocks from signals where the modulation profile is unknown or imperfect.
Spread spectrum clocking introduces some difficulties for CDR loop design. As data rates increase, communications performance is increasingly impacted by jitter in the locally recovered clock signal. At the same time, inter-symbol interference (ISI) and cross talk may also increase as the data rate increases. The local CDR circuit generally receives a noisier signal, and significant instants (for example, the zero crossing points of the waveform) may be blurred or otherwise adversely impacted by this interference and cross talk.
Referring now to FIG. 3A, a conventional CDR loop is shown. Phase detector 211 compares spread spectrum input signal 250 to recovered clock signal 255 to produce an unfiltered error signal 212. Loop filter 213 filters the error signal to reduce jitter, and provides a filtered error signal to signal generator 230. Signal generator 230 then generates the recovered clock from to the filtered error signal and (typically) a reference clock signal (not shown).
The error signal generated by phase detector 211 is generally a noisy estimate of the phase error (e.g., the error signal may comprise a desired error term and a noise term). The loop filter processes the phase error signal in order to generate a useful error while suppressing the effect of the noise as much as possible.
The bandwidth of the loop filter generally determines the range of error signal frequencies that the loop filter will pass. The value of this bandwidth typically has a direct impact on the performance of the CDR. For example, if the value of the loop bandwidth is large, the loop filter can pass a wide range of frequencies for the error signal. A wide loop bandwidth may therefore allow the CDR to track out large frequency errors (e.g., errors due to spread spectrum modulation of the input signal and frequency difference between the transmitter and receiver clocks). However, a loop with a wide bandwidth will also pass a wider portion of the noise spectrum, resulting in a noisy control signal for the signal generator and causing large phase jitter on the recovered clock.
In contrast, a small value for the loop bandwidth may limit the amount of noise that passes through the filter. The narrow loop bandwidth will generally result in a cleaner control signal for the signal generator. However, the drawback of using a narrow loop bandwidth is that the range of frequencies that the CDR loop can track is limited, thereby reducing its applicability to spread spectrum signals.
Another important design criterion for the loop filter is the order of the filter. FIGS. 3B and 3C, show conventional first-order and second order loop filters. Trade-offs between the frequency tracking capability and the noise filtering performance of the first order loop are typically made by adjusting Kp (e.g., at multiplier 261). SSC can make the first order loop unusable because of an unacceptably large frequency variation. When the frequency difference between transmitter clock and receiver clock is substantially constant, the second order loop generally separates frequency tracking and noise filtering by including a frequency loop (e.g., multiplier 265, adder 266 and delay 267). However, for SSC recovery where frequency varies in a periodic manner, the second order loop still suffers from tracking this frequency variation.
A need therefore exists for stable, reliable recovery of spread spectrum clock signals from spread spectrum data signals with good noise resistance at high data rates.